Stability considerations for Miller Compensated Transimpedance Stages
Investigation #1 - An op-amp with a push-pull transimpedance stage
The op-amp circuit is modelled with an ideal input stage, and ideal output stage, configured with a closed loop gain of 20dB and a unity loop gain frequency of approximately 800 kHz by the 100pF Miller compensation cap and the 5mA/V input stage transconductance.
For the purpose of investigating the Miller loop gain and phase response the global feedback loop is disabled for AC by L1 and the loop gain probe is placed in series with Cmiller.
Here is the result:
The Miller compensation loop is not stable - the unity loop gain frequency is 100 MHz (Eeekk!) and the phase margin is about zero.
#1 - increase the TIS load capacitance (Cshunt) from 20 pF to 500 pF to kill the HF loop gain of the TIS. Note that Cshunt does not add another "pole" to the response - as far as the output node of the TIS is concerned, it is just an additional amount of capacitance effectively in parallel with Cmiller.
Now that looks a bit better! The unity loop gain frequency has been reduced to a bit under 20 MHz and the phase margin is better than 60 degrees. The TIS is comfortably stable.
The TIS is now stable, but with what compromise? 500 pF is a lot of capacitance to plonk at the output node of the TIS and will cause a lot of unnecessary distortion at high frequencies due to the additional loading. A very important observation however: TIS stability can depend very much on there being a large shunt compensation capacitance present at the output node.
In a power amplifier, this shunt capacitance can be provided by the input capacitance(s) of the driver transistors of the power output stage; A possible advantage of a "Double EF" output
stage over a "Triple EF" output stage - keep in mind that a TIS driving the latter may need to be augmented with Cshunt for Miller compensation loop stability reasons.
As theory predicts, we have the same level of stability in the Miller compensation loop with ten times less Cshunt. Yahoo.
But is there a trade off? Yes - the output impedance of the TIS will not be as low throughout the audio frequency range due to both the increased emitter degneration of the common-emitter
voltage gain stage(s) and the reduced loop gain. However this is the price one pays for a healthy phase margin and stability. It's worth noting that the simulation as present thus far is a
simplified one that does not take into account aspects of PCB layout. However, in practice, I have found it to be an entirely reliable predictor of performance and stability, for practical
PCB layouts using either SMD or through hole components so long as the unity loop gain frequency of the Miller compensation loop is conservatively designed to be in the region of 10 to 20 MHz,
which quite suffices for any audio application.