An Ultra Low Distortion State Variable Oscillator

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An advanced low distortion oscillator design based on the state variable topology originally described in Ref [1], that was the basis for the Audio Precision System 1 Generator section, as well as that of the THD analyzer described by Cordell in Audio July, August 1981.

The design here uses current generation low low noise, ultra low distortion op-amps from the National LME range. A four-phase rectifier makes uses of the state variable quadrature signals for the purpose of minimizing ripple in the amplitude control loop. Amplitude balance of the four phase rectifier is trimmed by a separate multiplexer-switched trimpot for each of the four decade ranges. This is compensates for the small amplitude imbalance between the quadrature sinewaves that results due to (primarily) the integrator capacitor tolerances.
Timing components and frequency calibration trimpots are switched by small signal relays. Frequency coverage is from 10 Hz to 50 kHz and is covered by 12 spot frequencies in 1, 2, 5 steps, with frequency selection achieved by means of a decoded 12-position rotary switch. To minimize trimpot wiper distortion, those in the signal path only conduct a small percentage of the signal current.

With the exception of the four-phase rectifier, the amplitude servo is essentially as per that described by Cordell with the following important modifications. Taking advantage of the lower input voltage noise of the LME op-amp, component values of the analogue multiplier stage (U1) are revised for a signal input voltage (to the multiplier) of 20 mV peak instead of 40 mV (as per the AP S1, incidentally). This lowered voltage, as impressed across the MMBF4091 JFET, helps further reduce distortion. The LME opamps used here, as opposed to the NE5534's, have a lower input voltage noise specification of 2.7nV sqrt/hz versus 4nV sqrt/hz. It is posssible that the 20mV peak jfet voltage could be reduced even further, for even less jfet distortion without too much additional noise, with a revision of the analogue multiplier resistor values, but I have erred on the conservative side just to start with. There will be some room for experiment/tweaking here, to find the optimal distortion signal to noise ratio.

The voltage reference for the error amplifier (U8) is derived from a buffered/filtered shunt voltage regulator instead of from the +15V rail with a resistive divider, preventing power supply noise/variations modulating the amplitude control voltage. Frequency coverage is in four decade ranges. On the lowest range, a x10 larger capacitance is switched into the rectifier filter circuit to reduce the ripple in the amplitude servo loop. I found it a rather unnecessary complication to switch in a different time constant for each of the four decade ranges, as per the Cordell design, as the amplitude settling time on the second lowest decade range is actually quite quick when switching frequency within that range. Maintaining the same time constant for the upper decade ranges ensures that the amplitude control loop ripple at progressively higher frequencies is attenuated to a much greater degree, which can only benefit the oscillators distortion performance. It needs to be kept in mind that the amount of additional distortion introduced by the amplitude control loop is simply a trade off with amplitude settling time. With a slow enough servo loop time constant, even the ripple of a half wave rectifier could be made to contribute a entirely negligible amount of aditional distortion, but one generally wouldn't want to wait around for the amplitude to settle each time the operating frequency is switched on the lowest decade range.
The four-phase recitifier that I have designed into the servo control loop of the design presented here, provides a dramatic reduction of servo loop ripple over even a basic fullwave rectifier, and is well worth the extra complication. In the setting of the servo loop time constant, once again erring on the safe side just to begin with, I have specified component values giving a rather conservative servo loop response. To yield the full benefit, in terms of amplitude servo loop settling time, of the four phase rectification, some experimentation will be required to see how much the time constant can be reduced before ripple in the amplitude control loop begins to contribute measurably to the oscillators total distortion.

A 50-ohm / 150-ohm / 600-ohm balanced line driver amplifier with variable + relay-switched amplitude ranging will be accommodated on a separate PCB

The actual distortion performance of the oscillator is currently below my measurement set up capability. I am currently assembling the distortion residual "motherboard" of my T.H.D. Analyser project and fabricating the custom instrument chassis, and will be in a position ot report on the preliminary oscillator distortion performance once done.

[1] Bruce E. Hofer "A Comparison of low frequency RC oscillator topologies", AES preprint #1526, NOV 1979.

Click here for the schematic diagram

Update 8 Jan 2012

I've had some excellent help with the development of this oscillator by Dimitri Danyuk, who built up a version of the oscillator and checked its performance on an AP SYS-2702. The oscillators performance was initially a disappointment, but through some great detective work and a few subsequent grounding track modifications to the PCB, the distortion performance ended up rivaling the performance of the AP's signal generator section - and investigations at the time of writing suggest that there is significant scope for further improvement with a revision (slowing down) of the amplitude control loop time constant.

I made a couple of mistakes with the grounding layout which compromised performance. Firstly, I originally intended to keep the signal ground and power (supply bypass) ground planes completely seperate. The general idea was to prevent any possibility of fluctuations on the supply rail voltages from injecting currents into the signal ground via the op-amp supply pin bypassing capacitors. This is a technique I have used many times in the past with success in various designs utilizing comparatively "slow" op-amp types, but it turns out that this was a mistake for a PCB layout with the >50 MHz GBWP LME op-amps. The inverting stages of the state variable filter, that being the summing amplifier and the two intergrator stages, did not appreciate having their non-inverting inputs returned to the star ground point via the impedance of a common, independent ground plane strip. The inductance of this ground plane strip was high enough so the the inverting stages happily talked to each other and oscillated merrily at 40 MHz or so. This compromised the distortion of the oscillator to the extent that on no frequency setting did the THD performance better -100dB. This problem was cured simply by cutting the PCB tracks for the non-inverting op-amp input pins and connecting them directly to the ac-bypassed "power" ground plane instead.

Another mistake I made was underestimating the degree to which the ground return ripple currents from the 4-phase rectifier contaminate the signal ground return for the amplitude control loop. In my PCB layout, the distortion sensitive multiplier stage shares a common signal ground plane with the 4-phase rectifier - the rectifier circuit being "up stream" from the star ground. I really thought that the impedance of the amplitude control loop signal ground plane would be low enough to make the rectifier ground return currents negligible in effect, but not so. By lifting both the source pin of the multipliers JFET (Q1) and resistor R5 from this contaminated ground plane, and returning them instead to the PCB's star point with a short length of wire, the oscillators distortion performance was significantly improved, to the extent shown in the AP plot pictured below.
The amplitude control loop servo (U10) and the voltage reference circuitry (VREF1, U9), however, are still riding on the contaminated signal ground plane with the up-stream 4-phase rectifier, and there are still significant (measured) high order products making their way to the JFET gate.

Besides these grounding modifications, Dimitri also made a small modification of substituting resistor R1 with a 1k resistor in series with a 2k trimpot. This allowed the ratio of ac signal fed back to the gate of the jfet to be adjusted for optimal distorion cancellation, which proved to provide a measurable improvement to the measured THD. Due to measurements taken thus far, it is evident that the oscillators THD could be lowered further still by slowing down the amplitude control loop - at the extremely low distortion level currently achieved, the residual ripple of the 4-phase rectifier does still appears to be a limiting factor.

I'm currently working on a comprehensive revision of the PCB to correct all of the grounding issues detailed above, as well as a few refinements such at the additional trimpot to adjust the jfet ac gate voltage. Stay tuned (but please don't hold your breath, I'm very busy with many other things).

Please note that this is not a "final" measurement, just a quick and dirty run of an experimental prototype. Spurious and birdies at strange frequencies at ~ -140dB levels can be put down to CF lights, DSO power supplies, soldering station RFI, aliens tunneling underground, etc, etc......
The Distortion+N result picture above was achieved with the amplitude of oscillation set to only 900 mV rms. I was originlly concerned about capacitor (intergrator) distortion, so I set the amplitude relativiely low. However from the results attained thus far, it seems the amplitude could be raised considerably before the capacitor distortion become dominant. I'm changing component values in the revised version to raise the amplitude of oscillation to 2 V rms. This will see a 6.9dB drop in the noise floor.

Update 29 Jan 2012

I have finally completed the revised PCB layput to resolve the issues described above, along with a few other modifications. The grounding scheme has been completely re-worked, with the 4-phase rectifer circuit having its own completely seperate ground plane. I have also included a unity gain instrumentation op-amp into the circuit (U8, INA111) to differentially sense the 4-phase rectifier voltage directly across the terminals of the output capacitor (C11 & C12). This permits the greatest isolation of signal noise between the seperate ground planes. Anf there now a trimpot (RV9) to adjust the multiplier jfet (Q1) gate signal voltage for minimum jfet distortion.

I've also changed most of the components to surface mount and reduced the board size, although the layout is still very homebrew friendly. The only components I did not change to SMD types are the R's and C's of the state variable filter and multiplier and a few small electrolytics. The amplitude of oscillation has been increased from ~1 Vrms to 2 Vrms. I've also reduced the resistor values for the "loop inverter" stage 2.6 times for perhaps a small reduction in noise.

Click here for the revised schematic diagram

Update 26 Feb 2012

I've been a bit busy the last month building/planting veggie gardens and completing a tube amplifier, so this project has been sitting on the back burner. I currently have the new PCB 98% loaded and it's almost ready to go. I've made a few minor revisions to a few of the component values and have uploaded the revised oscillator schematic, downloadable via the old link above.

I've got a parts order going for the rest of the bits, along with a few other parts I need to get my THD analyser project up and running. I intend to get stuck into this project properly now in the coming weeks. As stated previously, this oscillator board is to be the "generator" part of the THD analyser project. I've made a number of changes to that projects wiring/grounding and power supply configuration. On my webpage devoted to the THD analyser project a preliminary (and now partly obsolete) schematic for the differential line driver / amplifier, which is to be mated to this oscillator module can currently be downloaded.

A major problem in a project like this, when striving for distortion components <120dB, is mitigating ground loops between the various PCB's. For example, the line driver board must amplify the signal from the oscillator board as sensed directly at the signal & gnd output pins on the oscillator PCB. A ground loop problem arises, however, if both PCB's share a common power supply. If, for example, the signal output of the oscillator board is connected to the signal input of the line driver board with a length of coax having the shield terminated at only one end, then line driver board will amplify the oscillators desired signal output along (in summation) with the (undesired) potential difference induced across the oscillator PCB's power supply ground return wire, which of course carries the distorted signal currents of the 4-phase rectifier.

I have decided the best fix to the problem is to complement a signal ground lift on the line driver PCB by having completely seperate power supplies for each module, such that the only ground connection between oscillator PCB and the line driver PCB is the shield of the coax cable connecting the oscillator PCB's signal output to the line driver boards signal input (the shield terminated at both ends). The distortion metering circuitry of the THD analyser will have its own seperate power supply module as well.
I am currently laying out the regualted power supply module PCB's which individually use small PCB-mount toroid transformers. The sperate PSU modules for the oscillator board and the line driver board are accomodated on a single PCB, and these three PCB's in total will comprised the complete "Generator" section of the THD analyser; or they could, alternatively, be built up and installed into a single chassis by anyone wanting a general purpose, high performance audio oscillator with a variable amplitude, differential/single-ended signal output with a switchable 50 / 150 / 600 ohm output impedance. I will begin to revamp my THD analyser project page once these modules are built and tested.

Update 5 March 2012

It's Alive! The revised oscillator board is now completed and operational, and performance testing in conjunction with my THD analyser project thus far confirms that the performance is as expected. The oscillator works perfectly. The only hiccup was that the INA111 in-amp, which is listed as a "SOIC" on Element 14's (formerly Farnell) website, turned out to be in fact one of those damn annoying SOP-16 300-thou wide SO packages, so I had to mount it on my PCB's SOIC footprint at a 45 degree angle with the pads jumpered to the pins on one side of the chip with short (~5mm) lengths of tinned copper wire. But anyway, it's working. I'll be keeping this blog page up for the time being, but I won't be updating it any longer. All details and further developments will be posted, from now on, on my THD analyser project page, which itself will be re-written from a "development" blog to a comprehensive finished project description once the analyser project, which is currently progressing very promisingly, is completed.
BTW, please don't laugh at my scopes shown in the picture - they were both freebies (along with about 20 others)! I've been getting by with these only because my Rolls Royce analogue boat anchors keep developing faults that I haven't the time to continuously fix (if I intend to get any projects finished). So I have finally splurged out on a brand new 200 MHz, 2 Gs/s Rigol DSO, which will arrive in a week or so. 3-year warrantly, big colour display, FFT, blah, blah and about 1/3 the price of a comparable performance Tek. Yahoo.

Update 16 August 2012

This webpage is now obsolete. Full details of the oscillator, including the final schematic details, PCB gerber files, and performance measurements are to be found on my THD Analyser project page:

Click here